The ability to test the circuitry on an integrated circuit in an efficient manner is very important. Many integrated circuits, such as microprocessors and peripherals, use structured arrays such as programmable logic arrays (PLAs), random access memory (RAM), read only memory (ROM), and other array-type structures. In order to provide observability of these array-type structures, the output signals produced by the array must be transferred off the integrated circuit by way of one or more integrated circuit pins.
Most arrays produce multiple parallel outputs. It would waste a great deal of silicon area to route all of these parallel outputs directly to test circuitry or to integrated circuit pins. Instead, a serial shift path or scan path is used at the output of the array. The parallel array outputs are thus converted into a serial bit stream called the scan data output. The first parallel output signal becomes the first bit of the scan data output. The second parallel output signal becomes the second bit of the scan data output, and so on. Only a single output, the scan data output, must be routed from the array to test circuitry or to a pin.
Array structures typically require some type of bit line sensing circuitry for each output. A sense amplifier, or sense amp, is normally used to perform this bit line sensing function for each output. Each sense amplifier is then followed by a master/slave test latch in order to support the scan testing. The master/slave test latches are coupled together to form a shift register structure. These master/slave test latches are not used during normal operation, but are extra circuitry required only for testing purposes.
The scan testing of the array is performed in the following manner. First, an input stimulus is given to the array and the array is enabled. Second, each sense amplifier senses the state of its output Line and stores this value in its associated master test latch. Third, each master test latch shifts the output data into its associated slave test latch. Fourth, each slave test latch shifts the output data into the adjacent master test latch in the same direction.
The last slave test latch has no adjacent master test latch, but instead shifts its output data onto a data path that will lead to test circuitry. The test circuitry may be located on the integrated circuit, or may be a testing device that communicates with the integrated circuit through one or more pins. The third and fourth steps are repeated until all of the output data has been shifted onto the data path leading to the test circuitry. Then the procedure starts over again with the first step using a different input stimulus. In this manner, the output data is serially shifted, one bit at a time, to the test circuitry. The slave latches are used in order to prevent any of the latched data from being overwritten.
In order to reduce test circuitry, some array structures do not use master test latches, but instead use the sense amplifiers for dual purposes. Each sense amplifier is used as a sense amplifier and is also used to perform the latching function of a master test latch during scan testing. However, the slave test latch is still required to perform a second latching function.
The second, third, and fourth steps are performed in the following manner. For the second step, each sense amplifier senses the state of its output line and stores this value in its own circuitry. For the third step, each sense amplifier shifts the output data into its associated slave test latch. And for the fourth step, each slave test latch shifts the output data into the adjacent sense amplifier in the same direction. The third and fourth steps are repeated until all of the output data has been shifted onto the data path leading to the test circuitry. Unfortunately, this approach still requires slave test latches which are extra circuitry used only for testing purposes.